Packet communication networks are rapidly becoming a major vehicle for the transmission of digital data. These networks allow the sharing of expensive resources among a collection of "bursty" users and are especially well suited for the unique nature of computer-based communications. A packet is a collection of data bits which can be up to a few thousand bits in length. Each packet contains the necessary addressing and control information to allow the proper routing of the data through the network. A synchronization word, or unique word, is included in each data packet to enable a receiver such as in a satellite communication (SATCOM) system to acquire proper timing. The probability of successful acquisition by the receiving system is directly tied to the "uniqueness" of the synchronization word with respect to other data patterns and to the capabilities of the synchronization circuit.
The synchronization circuit must be able to distinguish synchronization words from random noise, radio frequency interference (RFI), and modem preamble bit patterns. Synchronization circuits, to be truly effective, must be flexible in the following areas:
(1) synchronization word lengths, PA0 (2) correlation error tolerance, PA0 (3) synchronization word bit patterns, and PA0 (4) blanking pulse length tolerance.
Therefore there exists a need for a programmable synchronization word detector for packet type communications wherein the detector is adaptable for different synchronization word types and lengths, has a variable maximum error rate and can reject data when there is intense RFI.